PDF) Detection of Delay Faults in Memory Address Decoders
PDF) Extending Internet into Space – ESA DTN Testbed Implementation and Evaluation
PDF) Accumulator-Based Weighted Pattern Generation.
PDF) High-Level Test Synthesis for Delay Fault Testability
PDF) A Closed-Loop Approach for Improving the Wellness of Low-Income Elders at Home Using Game Consoles
Education and Information Technologies | Home
PDF) Concurrent Self-Test with Partially Specified Patterns For Low Test Latency and Overhead
PDF) Survival analysis for modeling critical events that communities may undergo in dynamic social networks
PDF) Delay-Insensitive Cell Matrix.
PDF) Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique
PDF) Test pattern generation based on arithmetic operations
PDF) An adaptive BIST to detect multiple stuck-open faults in CMOS circuits
PDF) Detection of Delay Faults in Memory Address Decoders
ERCIM News 96 by Peter Kunz - Issuu
PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences
PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences
PDF) A Context-Aware Meeting Room: Mobile Interaction and Collaboration Using Android, Java ME and Windows Mobile
Steffen Tarnick's research works | Universität Potsdam, Potsdam and other places
PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences
PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences
PDF) Efficient Test Compaction for Pseudo-Random Testing
PDF) Symmetry Measure for Memory Test and Its Application in BIST Optimization
PDF) Multimode scan: Test per clock BIST for IP cores
